Several non-volatile memory technologies have been disclosed in prior art. For example, in U.S. Pat. No. 4,203,158, a non-volatile electrically alterable semiconductor memory devices is disclosed. In that device, electrical alterability is achieved by Fowler-Nordheim tunneling of charges between a floating gate and the silicon substrate through a very thin dielectric. Typically, the thin dielectric is an oxide layer with a thickness of less than 100 angstroms. However, such a device requires a floating gate transistor and a separate select transistor for each storage site. Thus, necessarily, each storage site or cell is large due to the number of transistors required for each cell. Further, another disadvantage is the reliability and manufacturability problem associated with the thin oxide tunnel element between the substrate and the floating gate.
U.S. Pat. Nos. 4,274,012 and 4,599,706 seek to overcome the program of reliability and manufacturability of the thin oxide tunnel element by storing charges on a floating gate through the mechanism of Fowler-Nordheim tunneling of charges between the floating gate and other polysilicon gates. The tunneling of charges would be through a relatively thick inter-polyoxide. Tunneling through thick oxide (thicker than the oxide layer disclosed in U.S. Pat. No. 4,203,158) is made possible by the locally enhanced field from the asperities on the surface of the polycrystalline silicon floating gate. Since the tunnel oxide is much thicker than that of the tunnel oxide between the floating gate and the substrate, the oxide layer is allegedly more reliable and manufacturable. However, this type of device normally require three layers of polysilicon gates which makes manufacturing difficult. In addition, voltage during programming is quite high and demands stringent control on the oxide integrity.
In the non-volatile semiconductor memory disclosed in U.S. Pat. No. 4,616,340, a select gate and a floating gate are formed on the surface portion of the substrate between a source region and the drain region also acting as a control gate through a gate oxide film. A part of a channel current is injected into the floating gate at the surface portion under the edge of the floating gate covered by the select gate.
U.S. Pat. No. 4,698,787 discloses a device that is programmable as if it were an EPROM and erasable like and EEPROM. Although such a device requires the use of only a single transistor for each cell, it is believed that it suffers from the requirement of high programming current which makes it difficult to utilize on-chip high voltage generation for programming and erasing. Further, it is believed that such a device requires tight distribution program/erase thresholds during device generation, which results in low manufacturability yield.
In U.S. Pat. No. 5,023,694, floating gates with sharp edges are illustrated where the edges facilitate the tunneling of electrons between the floating gate and the control gate.
In U.S. Pat. No. 5,029,130, a split gate single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulation layer over a portion of the channel region and over a portion of the drain region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate. Programming is accomplished by electrons from the source migrating through the channel region underneath the control gate and then by abrupt potential drop injecting through the first insulating layer into the floating gate.
U.S. Pat. No. 5,045,488 discloses a method for making an electrically programmable and erasable memory device having a re-crystallized floating gate. In that method, a substrate is first defined. A first layer of dielectric material is grown over the substrate. A layer of polycrystalline silicon or amorphous silicon is deposited over the first layer. The layer of silicon is covered with a protective material and is annealed to form re-crystallized silicon. A portion of the protective material is removed to define a floating gate region. Masking oxide is grown on the floating gate region. The remainder of the protective material with the re-crystallized silicon thereunder is removed. A second layer of dielectric material is formed over the floating gate and over the substrate, immediately adjacent to the floating gate. A control gate is patterned and is formed. The drain and source regions are then defined in the substrate.
The scaling limit to the memory cell size of some of the above described split gate technologies can be partially attributed to the dual functional role of the control gate where the control gate serves both as the control gate as well as the erase gate. When the control gate operates as the erase gate, the voltage applied to the control gate can be as high as 14 volts. Under such scenario, in order for the memory cell to behave properly, the gate oxide must be greater than about 200 Å. This gate oxide thickness requirement (under the control gate) limits the scaling of memory cells.
Therefore, it would be desirable to have a novel memory cell having a structure that does not have such a limit on the scaling of the memory cell. It would be also desirable to have a method for fabricating such a memory cell and array.